Imperas’ riscvOVPsim RISC-V reference model and simulator has been updated and extended for RISC-V vector instructions and now supports coverage driven verification ...

Imperas has extended its Risc-V reference model and simulator to cover forthcoming vector instructions and to support coverage-driven verification analysis. Called riscvOVPsim, the enhanced version ...

RISC-V chip designer SiFive is introducing two new processors that the company says are designed for high-performance, energy-efficient applications such as wearables, smart home devices, virtual ...

ARM has unveiled a new, highly flexible type of vector processing instruction that it plans to debut in HPC markets and businesses. Share on Facebook (opens in a new window) Share on X (opens in a new ...

A novel AI-acceleration paper presents a method to optimize sparse matrix multiplication for machine learning models, particularly focusing on structured sparsity. Structured sparsity involves a ...